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2010-2012 Microchip Technology Inc.
DS41417B-page 281
PIC16(L)F722A/723A
T
T1CON Register ......................................................... 19, 112
TMR1ON Bit.............................................................. 113
T1GCON Register............................................................. 113
T2CON Register ................................................. 19, 116, 164
Thermal Considerations.................................................... 208
Time-out Sequence............................................................. 32
Timer0................................................................................. 99
Associated Registers ................................................ 101
Interrupt..................................................................... 101
Operation ............................................................ 99, 104
Specifications............................................................ 217
Timer1............................................................................... 103
Associated registers.................................................. 114
Asynchronous Counter Mode ................................... 105
Reading and Writing ......................................... 105
Interrupt..................................................................... 108
Modes of Operation .................................................. 104
Module On/Off (TMR1ON Bit)................................... 113
Operation During Sleep ............................................ 108
Oscillator ................................................................... 105
Prescaler................................................................... 105
Specifications............................................................ 217
Timer1 Gate
Selecting Source............................................... 106
TMR1H Register ....................................................... 103
TMR1L Register........................................................ 103
Timer2
Associated registers.................................................. 116
Timers
Timer1
T1CON.............................................................. 112
T1GCON ........................................................... 113
Timer2
T2CON.............................................................. 116
Timing Diagrams
A/D Conversion......................................................... 219
A/D Conversion (Sleep Mode) .................................. 219
Asynchronous Reception .......................................... 140
Asynchronous Transmission..................................... 136
Asynchronous Transmission (Back-to-Back) ............ 137
Brown-out Reset (BOR) ............................................ 215
Brown-out Reset Situations ........................................ 31
CLKOUT and I/O....................................................... 213
Clock Synchronization .............................................. 173
Clock Timing ............................................................. 210
Enhanced Capture/Compare/PWM (ECCP) ............. 217
I2C Bus Data ............................................................. 224
I2C Bus Start/Stop Bits.............................................. 223
I2C Reception (7-bit Address) ................................... 168
I2C Slave Mode with SEN = 0 (Reception,
10-bit Address) ................................................. 169
I2C Transmission (7-bit Address).............................. 170
INT Pin Interrupt.......................................................... 38
Reset, WDT, OST and Power-up Timer ................... 214
Slave Select Synchronization ................................... 161
SPI Master Mode ...................................................... 158
SPI Master Mode (CKE = 1, SMP = 1) ..................... 221
SPI Mode (Slave Mode with CKE = 0) ...................... 160
SPI Mode (Slave Mode with CKE = 1) ...................... 160
SPI Slave Mode (CKE = 0) ....................................... 222
SPI Slave Mode (CKE = 1) ....................................... 222
Synchronous Reception (Master Mode, SREN) ....... 150
Synchronous Transmission....................................... 148
Synchronous Transmission (Through TXEN) ........... 148
Time-out Sequence
Case 1 ................................................................ 33
Case 2 ................................................................ 33
Case 3 ................................................................ 33
Timer0 and Timer1 External Clock ........................... 216
Timer1 Incrementing Edge ....................................... 108
USART Synchronous Receive (Master/Slave) ......... 220
USART Synchronous Transmission (Master/Slave). 220
Wake-up from Interrupt............................................. 182
Timing Parameter Symbology .......................................... 209
Timing Requirements
I2C Bus Data............................................................. 225
I2C Bus Start/Stop Bits............................................. 224
SPI Mode.................................................................. 223
TMR0 Register.................................................................... 19
TMR1H Register ................................................................. 19
TMR1L Register.................................................................. 19
TMR2 Register.................................................................... 19
TMRO Register................................................................... 21
TRISA ................................................................................. 48
TRISA Register............................................................. 20, 48
TRISB ................................................................................. 56
TRISB Register............................................................. 20, 57
TRISC................................................................................. 67
TRISC Register............................................................. 20, 67
TRISE ................................................................................. 74
TRISE Register............................................................. 20, 74
TXREG ............................................................................. 135
TXREG Register ................................................................. 19
TXSTA Register.......................................................... 20, 142
BRGH Bit .................................................................. 144
U
UA..................................................................................... 175
Update Address bit, UA .................................................... 175
USART
Synchronous Master Mode
Requirements, Synchronous Receive .............. 220
Requirements, Synchronous Transmission...... 220
Timing Diagram, Synchronous Receive ........... 220
Timing Diagram, Synchronous Transmission... 220
V
VREF. SEE ADC Reference Voltage
W
Wake-up Using Interrupts ................................................. 182
Watchdog Timer (WDT)...................................................... 29
Clock Source .............................................................. 29
Period ......................................................................... 29
Specifications ........................................................... 216
WCOL bit .................................................................. 162, 174
WPUB Register................................................................... 57
Write Collision Detect bit (WCOL) ............................ 162, 174
WWW Address ................................................................. 283
WWW, On-Line Support ....................................................... 8
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